The present invention relates to a semiconductor device and more particularly to an insulated gate field effect transistor having an SOI (silicon on insulator) structure.
An SOI-MOSFET (silicon on insulator--metal oxide semiconductor field effect transistor) formed on a thin single crystalline silicon layer on an insulated substrate can be integrated on a large scale on one substrate using a micro fabrication process for silicon. Furthermore, the SOI-MOSFET is suitable for high speed operation because the parasitic capacity of a formed transistor is smaller than that when a conventional single crystalline silicon substrate is used, so that it has been noticed.
A semiconductor device (MOSFET) using a conventional single crystalline silicon substrate biases the channel unit using a substrate electrode. On the other hand, the SOI-MOSFET cannot bias from the lower part of the channel because there is the insulated layer (or insulated substrate) at the bottom of the thin single crystalline silicon layer and there is a problem imposed that it is called a "floating substrate" causing an unstable operation.
Namely, it is reported that the NMOS (N channel MOS) generates a large leakage current in the off state because holes are accumulated in the channel unit and causes a kink (kink effect) in the current characteristic even in the on state. It is known that this problem appears remarkably in an NMOS having a large impact ionization.
An art for solving this problem is disclosed, for example, in Japanese Patent Application Laid-Open 4-34980 and Japanese Patent Application Laid-Open 7-273340.
As described in IEEE Electron Devices Letters, Vol. 15, No. 12, pp. 510 to 512, December 1994, it is considered to bias the channel unit (P-silicon) via the gate electrode. The MOSFET having a structure that the substrate and gate are connected can be regarded as a device in which a FET and a lateral bipolar transistor coexist. It is reported that by such a MOSFET, a characteristic which is excellent particularly in low voltage operation (0.6 V max.) can be obtained.
FIG. 22 is a plane schematic layout showing the device structure disclosed in the aforementioned reference. The plane layout uses the same layout as that of the MOSFET formed on a conventional single crystalline silicon substrate. The characteristic of this structure is that a part of an active region 100 comprising a thin single crystalline silicon layer is patterned in the same shape as that of a gate (electrode) 500. At a contact 600 of the gate, the gate 500 and the active region are in contact with each other by wiring at the same time.
FIG. 23 shows only the active region 100 shown in FIG. 22 and at the contact portion of the gate, the active region is patterned in a so-called dog bone shape. The cross sectional structure of the contact is shown in FIG. 24. The cross sectional structure shown in FIG. 24 is a cross sectional view of the section AA. As shown in FIG. 24, the contact between the gate 500 and the active region 100 is realized by forming a contact hole piercing through the gate 500 and an oxide film 910 of the gate, allowing the active region 100 under the gate oxide film 910 to expose, and forming a metallic wire 700 in the contact hole.